1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly, to a semiconductor device equipped with an analog-to-digital (A/D) converter which operates with a low power supply voltage. More specifically, the present invention is concerned with a semiconductor device having an A/D converter equipped with a gate boost circuit which applies a boosted voltage to a gate of a transistor forming an analog switch of a sample and hold circuit in order to reduce the ON resistance of the transistor.
Recently, it has been required to develop a low power consumption, high density, high reliability, high quality semiconductor device in order to reduce energy consumed in electronic devices.
2. Description of the Related Art
In general, the A/D converter includes a sample and hold circuit, which is located in an analog signal input part and is made up of an analog switch and a capacitor. When the analog switch is ON, an analog input signal is applied to the capacitor of the sample and hold circuit. While the analog signal is being converted into a digital signal, the analog input voltage across the capacitor is maintained at a constant level. Hence, the analog signal can accurately be converted into the digital signal.
A ON/OFF control of the analog switch is carried out so that a sampling clock pulse is applied to the gates of transistors forming the analog switch at constant intervals. If the sampling clock pulse does not have a sufficiently high voltage, the analog switch will have a high ON resistance, which may cause the A/D converter to malfunction. By taking into consideration the above, the conventional A/D converter is equipped with a gate boost circuit, which boosts the voltage of the sampling clock pulse applied to the gates of the transistors forming the analog switch.
FIG. 1 is a circuit diagram of a sample and hold circuit 10 and a gate boost circuit 18, which circuits are provided in a conventional A/D converter. The gate boost circuit 18 is generally made up of a boost part 11, a level converter 12, a clamp part 13, and inverters 14, 15 and 16.
The boost part 11 is made up of a capacitor C1 and a P-channel field effect transistor P1 such as a MOS transistor. The source of the transistor P1 is connected to a power supply voltage VDD. A sampling pulse is applied to an input terminal a, and is boosted by a level approximately equal to the power supply voltage VDD due to the function of the capacitor C1 of the boost part 11.
The level converter 12 is made up of N-channel transistors Q2, Q3 and Q4 and P-channel transistors P5, P6 and P7. The level converter 12, which is provided at the output side of the boost part 11, outputs the high-level voltage of the sampling clock boosted by the boost part 11 as it stands, and converts the low-level voltage of the sampling clock into 0V. Due to the operation of the level converter 12, an analog switch 10a, which is made up of a P-channel MOS transistor P8 and an N-channel MOS transistor Q5, is supplied with the high-level and low-level signals certainly defined. Hence, the analog switch 10a is correctly turned ON and OFF.
The clamp part 13 is made up of an N-channel transistor Q1 and P-channel transistors P2, P3 and P4. As shown in FIG. 1, when the high-level signal is applied to the gate of the transistor Q1, the transistors P2, P3 and P4 are turned ON. Hence, a pass-through current can flow in the clamp part 13 from a node n3. If the clamp part 13 is not provided and the sampling clock has an excessively high voltage, the voltage of the node n3 is further boosted, the transistors connected to the node n3 will receive a voltage higher than the breakdown voltages thereof. The clamp part 13 allows the pass-through current to flow therein from the node n3 when the voltage of the node n3 becomes equal or higher than a predetermined level. Hence, the transistors connected to the node 3 can be prevented from being damaged.
The inverters 14, 15 and 16 function to invert the respective input signals and to shape the signal waveforms.
As shown in FIG. 1, the sample and hold circuit 10 is made up of the analog switch 10a and a capacitor C2 for the sample and hold operation. As described before, the analog switch 10a is made up of the transistors P8 and Q5. A node n6 of the gate boost circuit 18 is connected to the gate of the transistor Q5, and a node n5 thereof is connected to the gate of the transistor P8.
The two inverters 14 and 15 are provided between the input terminal a and the gate of the transistor Q5, while only the inverter 16 is provided between the input terminal a and the gate of the transistor P8. Hence, the transistors Q5 and P8 are simultaneously turned ON and OFF. When the sampling clock is at the high level, the transistors Q5 and P8 are both ON, and thus the analog switch 10a is ON. Thus, an analog input signal applied to an input terminal b reaches the capacitor C2. When the sampling clock is at the low level, the transistors Q5 and P8 are both OFF, and thus the analog switch 10b is OFF. Thus, the signal voltage applied to the capacitor C2 before the transistors Q5 and P8 are turned OFF is held in the capacitor C2.
As described above, the ON resistance of the analog switch 10a can be reduced by boosting the sampling clock pulse for controlling the analog switch 10a by the gate boost circuit 18. Further, the clamp part 13 prevents the boosted voltage of the sampling clock pulse output by the boost part 11 from exceeding the predetermined level and prevents the transistors from receiving a voltage exceeding the breakdown voltages thereof.
However, the circuit shown in FIG. 1 has a disadvantage in that the pass-through current flows in the clamp part 13 while the sampling clock pulse is at the high level and power is consumed for the above period. This is because the sampling clock pulse is directly applied to the gate of the transistor Q1 which functions as the switch provided in the clamp part 13.
There is another disadvantage as described below. The transistors Q5 and P8 may made to have a comparatively thick channel width in order to prevent occurrence of differences in the performance of the individual A/D converters due to errors caused in the production of transistors forming the A/D converters and to reduce noise. However, an increase in the channel width increases the threshold voltages of the transistors. Hence, use of transistors having a comparatively wide channel width makes it difficult to produce A/D converters which can operate with a relative low driving voltage. Particularly, it is very difficult to reduce the channel width of the transistor P8, which is not connected to the gate boost circuit 18 and receives the not-boosted signal via the gate.